Integrated circuits are often formed using an application specific integrated circuit architecture, which tends to reduce the design costs of the integrated circuit by using predetermined logic blocks in a somewhat customized arrangement to produce an integrated circuit according to a customer's specifications. However, memory architecture for such devices has remained substantially unchanged, with most memories either being completely customized or adapted to use a previously designed memory as is, where a customer's memory design cannot be tiled in more than one memory within the integrated circuit.
What is needed, therefore, is a memory tiling architecture where a customer's memory design can be tiled in more than one memory within the integrated circuit, and most preferably, memory mapping and tiling can be done automatically.